SRAM cells are popular for applications in which speed and/or low power consumption are important. For instance, large scale integrated circuits incorporating an L1 or L2 cache would benefit from using SRAMs. However, because of the number of transistors (and therefore real estate consumed), adding SRAMs into large LSIs has been difficult. Because of the large size of each SRAM cell and the number of cells required to be a functioning cache, the size of the LSI can be heavily dependent on the SRAM unit cell size.
The minimum width of device separation in SRAMs has conventionally been large, thereby hindering the adoption of SRAMs in LSIs.